When designing a semiconductor circuit, it is of great value to be able to reduce power consumption and increase the operating frequency of the circuit. However, increasing the operating frequency often makes some power saving techniques difficult or impossible to implement. For many circuits including sequential logic devices such as flip-flops and latches, power saving techniques may be scaled back or removed from a design in order to achieve the maximum frequency possible.
Since many semiconductor circuit designs will support a range of frequencies, the power saving techniques removed in order to achieve high frequencies could have been implemented for low frequency applications. In some cases, two separate designs can be implemented, one for low frequencies with enhanced power savings and one for high frequencies with reduced power savings. However, multiple such designs increases cost due to design creation, maintenance, and manufacturing, and reduces the flexibility of any one design.
Accordingly, what is needed is a single circuit design that can provide both high frequency operation with higher power consumption and power saving operation at lower frequencies for sequential logic devices. The present invention addresses such a need.